Electronics Industry

Applications of CFD tools in PCB, Board-level and Chassis Level Thermal Simulations

Electronics Cooling

Table of Contents: THERMAL CHARACTERIZATION OF IC PACKAGES | MOSFET | The Gerber file | ICEPAK: Basic Solver Setting | Heat Transfers in Fins | Thermo-Electric Cooling | Thermal Simulations in Data Centres | EMN-EMP Files | FPGA

There are vast range of applications of thermal simulations in electronics industry dealing with Printed Circuit Board (PCB), IC Chips, Diodes, MOSFET, FPGA, Power Transistors, Bipolar and Darlington Transistors, IGBT, Capacitors, Power Supply, Power Switches, Controllers, Inductors, Solid State Relays... In addition to board and chassis level simulation, thermal management of data centres include specialized cooling methods like heat sinks, TEC (Thermo-Electric Cooling), heat pipes, PCM (Phase Change Material), heat spreaders... A thermal network model for MOSFET-on-PCB is shown below. The applications include Synchronous Step Down Switcher, Synchronous buck converter, Inverting Buffers / Drivers, DC/DC Controllers...

Equivalence of Radiative Heat Transfer Rate at Low Temperature and Small Temperature Differences

Radiative heat flux rate: q_RAD'' = ε x σ x [T_W1⁴ - T_W2⁴] = ε x σ x [T_W1 - T_W2] x [T_W1 + T_W2] x [T_W1² + T_W2²]

Comparing the two equations: h_RAD ≡ ε x σ x [T_W1 + T_W2] x [T_W1² + T_W2²]

  For ε = 1.0, T_W1 = 80 [°C] and T_W2 = 40 [°C], h_RAD = 8.41 [W/m².K]

  For ε = 1.0, T_W1 = 60 [°C] and T_W2 = 50 [°C], h_RAD = 8.01 [W/m².K]

As you can see, the convective heat transfer coefficient in natural convection with air ranges between 5 to 15 [W/m².K]. Hence, the contribution of radiation in natural convection cases (such as electronic cooling) is approximatly equal to the convective heat transfer rate. In other words, convection and radiation contribute almost equal in natural convection heat transfer cases dealing with low temperature differences.

In general, the heat dissipation through the bodies of devices become difficult when the volume density of heat generation rate exceeds 10⁸ [W/m³]. Such devices are often connected to the PCB with thermal vias having thickness ~ 0.5 [mm].

Types of Simulations

• PCB or Package Level: Detail modeling of copper traces, thermal vias and dielectric material inside the PCB panel.
• Board Level: PCB modeled as simplified orthotropic thermal conductivity.
• Chassis Level: Similar to board-level simulation, bigger in computational domain.
• Rack Level such as in Data Centres: Most of the heat sources are modelled as lumped blocks.

Four ways PCB are modeled in ICEPAK

1. Hollow PCB: useful only in concept stage
2. Compact PCB: all layers lumped in a single isotropic material (orthotropic thermal conductivities in all 3 directions)
3. Detailed PCB: Each layer of PCB modeled with 'UNIFORM' thermal conductivity of that layer, calculated as volume weighted average of copper and substrate (FR4)
4. ECAD PCB: ECAD files with detail traces and vias.
   • Actual geometry of the traces and vias are not meshed along with the rest of the CFD model
   • Each of the metal and dielectric layer is modeled separately
   • Effect of the traces and vias is modeled in each of the CFD mesh cell by computing orthotropic thermal conductivity for the imported traces and vias.

Heat Generation and Heat Transfer Path

The effect of radiation heat transfer is very important in natural convection, as it can contribute to approximately 25% of the total heat dissipation. Unless the components are facing hotter surface nearby such as enclosure, the radiative heat transfer must be accounted for.

Construction Features on IC Packages

Die: It designates the piece of semiconductor on which all the active circuits lie. Dies are made of Silicon (110 – 150 W/m.K) or Gallium Arsenide (GaAs, 45 – 60 W/m.K) is used in special applications such as microwaves. The circuitry is present within a thin layer on one side only, known as active surface. The concept of "junction temperature" applies to the top surface of the die. The heat flux in the die and die-attach is very high, the junction temperature is very sensitive to the thermal conductivity and the thickness of the die and die-attach.

The Die is often attached to the substrate or the die pad by an adhesive known as the "die attach" which is made of an epoxy based compound having thickness 0.025 - 0.050 [mm] and thermal conductivity in the range 1 - 2 [W/m.K]. The semiconductor material of a die has a conductivity approaching that of a metal. If the active layer is assumed to generate constant power per unit area (an assumption that may not always be valid), the die will be practically isothermal. In practice, applications exist for which the heat flux varies significantly across the die, in which case a temperature gradient may exist on its active surface. For most packages, the thermal resistance offered by the die is small in comparison with that offered by the rest of the package. Referecnce: FloTHERM Pack User's Guide

Due to low thickness of the "die attach", it causes very little heat spreading. At the same time, it offers significant thermal resistance in out-of- the-plane direction due to its poor thermal conductivity value. Si is very widely used because of its cheap price, easiness in processing and fairly high thermal conductivity. SiC is an alternative material [though very costly] that has high thermal conductivity of 370 [W/m-K].

Die Pad or Die Flag: The Die is placed in insulated boxed often plastic packages, on a thin metal plate (made of copper and larger than the die) known as the die flag or die pad. It helps both in the manufacturing and thermal (heat dissipation) function. The metallic die flag acts as an effective heat spreader due to very high thermal conductivity of copper which can reduce the thermal resistance of a package by up to 15%.

Bond wires, made of Gold or Aluminum having diameter of the order of 0.025 [mm], are characteristics of wire-bonded packages. The number of bond wires in an IC package are of same order as the number of external leads/pins. Excerpts from "FloTHERM Pack User's Guide": In most ceramic packages, a negligible portion of the heat from the Die flows to the substrate through the bond wires. However, in plastic packages this may not be the case. Bond wires play a significant role in the heat transfer within peripheral leaded packages such as the PQFP. In area-array plastic packages such as the PBGA, bond wires can be important, especially for a 2-layer substrate.

Encapsulant: Also known as 'Overmold', it is an epoxy based compound with a thermal conductivity 0.6 - 0.7 [W/m.K].

Reference: FloTHERM PACK User Guide

THERMAL CHARACTERIZATION OF IC PACKAGES

1. The junction temperature is represented with a single temperature node.
2. The thermal flow path is represented by a thermal resistance network.
3. Junction Node represents the thermal source of the chip.
4. Case Node represents the upper surface of the package.
5. Board Node represents the circuit board temperature at a position of 1 [mm] from the edge of the device.
6. Two thermal resistors are connected between "the junction and the case" and between "the junction and the board".

Two-resistor model is a relatively simple model achieved by dividing a package vertically at the junction and is good for single function devices. However, this model has the least precise as compared to multi-resistor network and detailed thermal models. This model (like any thermal resistor model) does not support "Transient Analyses". The methods of thermal resistance measurement are described for θ_JB in JEDEC Standard JESD51-8 and for θ_JC in JESD51-14.

In general, thermal resistance Θ or R_TH = ΔT / P where P is power dissipation from the chip package in [W] and ΔT = T_J - T_A.

• Θ_JA: also designated as R_ΘJA, it is the thermal resistance from Junction to Ambient, measured as [K/W]. Ambient is a generic term to thermal 'ground'. This value depends on the package design, PCB, and heat transfer modes (airflow, radiation). As per "Semiconductor and IC Package Thermal Metrics" by Texas Instruments, it is a measure of the thermal performance of an IC package mounted on a specific test coupon.

  The standard test conditions are specified by Joint Electron Device Engineering Council (JEDEC) such as JESD15-3: Two-Resistor Compact Thermal Model Guideline, JESD51: Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device), JESD51-9 "Test Boards for Area Array Surface Mount Package Thermal Measurements" and JESD51-12: Guidelines for Reporting and Using Package Thermal Information.

  As described in webinar "Understanding Datasheet Thermal Parameters and IC Junction Temperatures" by Monolithic Power Systems - Θ_JA is valid only for its defined PCB and it is not a constant which can be used on all PCBs. Θ_JA allows comparison of different packages on a common PCB.

  As per datasheet for LTM8023: "θ_JA is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as still air although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition."

  Another use of R_JA or Θ_JA, is to calculate parameter called derating factor when the power dissipation values are unspecified in the datasheet. Using the formula T_J = T_A + P × Θ_JA, the permissible heat generation rate can be estimate for various ambient temperatures say between 25 [°C] to 75 [°C].

• Θ_JC: also designated as R_ΘJC, it is the thermal resistance from Junction to Case where case is a specified point on the outside surface of the package. It depends on the thermal conductivity of package materials (the lead frame, mold compound, die attach adhesive) and on the specific package design (thickness of the die body and die attach, exposed pads and internal thermal vias). Θ_JC considers only the resistance of heat flow paths to the surface of the package and hence represents only the conductive heat transfer path thermal resistance. EIA/JESD51-1 defines R_ΘJC as "the thermal resistance from the operating portion of a semiconductor device to outside surface of the package (case) closest to the chip mounting area when that same surface is properly heat sunk so as to minimize temperature variation across that surface".

  As described in datasheet for LTM8023: "θ_JCbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical μModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θ_JCtop is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical μModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ_JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application."

• Θ_CA: it is the thermal resistance from Case to Ambient. Thus: Θ_JA = Θ_JC + Θ_CA
• Ψ_JB: junction-to-board thermal-characterization parameter and Ψ_JT: junction-to-top thermal-characterization parameters are the "characterization parameters" that measure temperature change between the junction temperature and the temperatures of the board and top of the package respectively. These are not thermal resistances in true sense though they are useful to estimate the junction temperature when the temperature on top of the package or the board and the power dissipation are known.

  As described in datasheet for LTM8023: "θ_JB is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the μModule regulator and into the board, and is really the sum of the θ_JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9."

Example Calculation - 1: A transistor with power rating of 10 [W] and internal thermal resistance of 1.5 [K/W] has a case temperature of 60 [°C]. What is the actual value of junction temperature?

• Junction-to-case resistance: Θ_JC = 1.5 [K/W]
• Heat generation rate ≡ Power dissipation rate: P = 10 [W]
• Case temperature: T_C = T_J - P × Θ_JC. Thus: T_J = 60 [°C] + 10 [W] × 1.5 [K/W] = 75 [°C]

Example Calculation - 2: A chip with 5 [W] rating has a maximum junction temperature of 120 [°C] and an internal resistance of 0.5 [K/W] at an ambient of 40 [°C] with aluminium oxide wafers. What is the maximum permissible thermal resistance of the heatsink?

• Junction-to-case resistance: Θ_JC = 2.5 [K/W]
• Heat generation rate ≡ Power dissipation rate: P = 5 [W]
• Junction temperature: T_J = 120 [°C] As a "margin of safety", the permissible limit of junction temperature should be reduced by 20-30 [°C] from the value specified by the manufacturers.
• Ambient temperature: T_A = 40 [°C]. In case of natural convection (passive cooling) arrangment, due to the rise in temperature caused by heating of air between adjacent fins of the heatsink, the effective value of T_A should be increased by a margin of 10-20 [°C].
• Junction temperature: T_J = T_A + P × [Θ_HS + Θ_JC]. Thus: 120 [°C] = 40 [°C] + 5 [W] × (Θ_HS + 0.5 [K/W]). Hence, Θ_HS = 15.5 [K/W]

Excerpts from "Semiconductor and IC Package Thermal Metrics" by Texas Instruments: R_ΘJA is a variable function of not just the package, but of many other system level characteristics such as the design and layout of the PCB on which the part is mounted. In effect, the test board is a heat sink that is soldered to the leads of the device. Changing the design or configuration of the test board changes the efficiency of the heat sink and therefore the measured R_θJA. In fact, in still-air JEDEC-defined R_ΘJA measurements, almost 70 ~ 95% of the power generated by the chip is dissipated from the test board, not from the surfaces of the package. Because a system board rarely approximates the test coupon used to determine R_ΘJA, application of Θ_JA using

[T_J = T_A + R_ΘJA × P]

The document further elaboarates: "In light of the fact that R_ΘJA is not a characteristic of the package by itself but of the package, PCB and other environmental factors, it is best used as a comparison of package thermal performance between different companies. For example, if TI reports an R_ΘJA of 40 [°C/W] or 40 [K/W] for a package compared to a competitor's value of 45 [K/W], the TI part will likely run 10% cooler in an application than the competitor's part." As a "margin of safety", the permissible limit of junction temperature should be reduced by 20-30 [°C] from the value specified by the manufacturers.

Excerpts from "Thermal Design Basics" by Analog Devices: In ICs, one temperature reference point is always the device junction, taken to mean the hottest spot inside the chip operating within a given package. The other relevant reference point will be either T_C - the case of the device, or T_A - that of the surrounding air. This then leads in turn to the above mentioned individual thermal resistances Θ_JC and Θ_JA. Taking the most simple case first, Θ_JA is the thermal resistance of a given device measured between its junction and the ambient air. This thermal resistance is most often used with small, relatively low power ICs such as op-amps, which often dissipate 1 [W] or less. Generally, Θ_JA figures typical of op-amps and other small devices are on the order of 90-100 [°C/W] for a plastic 8-pin DIP package, as well as the better SOIC packages.

Excerpts from a datasheet: "The LTM8023MP is guaranteed to meet specifications over the full –55 °C to 125 °C temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors."

FPGA: Field Programmable Gate Array

Virtex UltraScale and Virtex UltraScale+ are, ASIC-class architecture, FPGA product family from AMD. Excerpts from UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575): "Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in a user application is not known to the component supplier. Therefore, it remains a challenge for AMD to predict the power requirements of a given FPGA when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, AMD offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements." The document further contains thermal resistance data with following notes: "The data includes junction-to-ambient in still air, junction-to-case, and junction-to-board data based on standard JEDEC four-layer measurements. The data in Table 10-1 is for device/package comparison purposes only. Attempts to recreate this data are only valid using the transient 2-phase measurement techniques outlined in JESD51-14. This data is not to be used in place of thermal simulation. Instead, refer to the thermal models provided for each device." In the chapter "Thermal Management Strategy", the document elaborates: "These resistances are measured using a prescribed JEDEC standard that might not necessarily reflect your actual board conditions and environment. The quoted θ_JA and θ_JC numbers are environmentally dependent, and JEDEC has traditionally recommended that these be used with that awareness."

Thermal interface material is needed because even the largest heat sink and fan cannot effectively cool an UltraScale or UltraScale+ device unless there is good physical contact between the base of the heat sink and the top of the UltraScale or UltraScale+ device. The surfaces of both the heat sink and the UltraScale or UltraScale+ device silicon are not absolutely smooth. This surface roughness is observed when examined at a microscopic level. Because surface roughness reduces the effective contact area, attaching a heat sink without a thermal interface material is not sufficient due to inadequate surface contact.

AMD advises against direct use of the θ_JC parameters to determine the thermal performance of the device in your application. The calculation of these parameters are done in accordance with the JEDEC standard JESD51 where system parameters differ greatly from most applications. Instead, run thermal simulations of the system in worst-case environmental conditions using Delphi thermal models, which more accurately represent the device thermal performance under all boundary conditions.

Efficiency and Power Losses in MOSFETS

Reference: MOSFET power losses and how they affect power-supply efficiency - by By George Lakkas, Product Marketing Manager, Power Management

MOSFETs have a finite switching time, therefore switching losses come from the dynamic voltages and currents the MOSFETs must handle during the time it takes to turn on or off. MOSFET switching losses are a function of load current and the switching frequency of power supply. There are 3 types of losses: conduction losses, switching losses and static (quiescent) losses.

Most of the power is in the MOSFET gate driver. Gatedrive losses are frequency dependent and are also a function of the gate capacitance of the MOSFETs. When turning the MOSFET on and off, the higher the switching frequency, the higher the gate-drive losses. This is another reason why efficiency goes down as the switching frequency goes up.

• JESD51: Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device)
• JESD51-1: Integrated Circuit Thermal Measurement Method—Electrical Test Method (Single Semiconductor Device)
• JESD51-2: Integrated Circuit Thermal Test Method Environmental Conditions—Natural Convection (Still Air)
• JESD51-3: Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-4: Thermal Test Chip Guideline (Wire Bond Type Chip)
• JESD51-5: Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms
• JESD51-6: Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air)
• JESD51-7: High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-8: Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board
• JESD51-9: Test Boards for Area Array Surface Mount Package Thermal Measurements
• JESD51-10: Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
• JEDEC51-12: Guidelines for Reporting and Using Electronic Package Thermal Information

Commercial Tools for PCB Design and thermal simulations

• ANSYS ICEPAK: A customized GUI for pre- and post-processing but uses FLUENT as solver.
• SIEMENS FloTHERM: similar in look and operation like ICEPAK with primitives, SmartPart and attributes.
• Electrical Packages such as PSPICE and Cadence (new owner of 6SigmaET): These packages primarily meant for design of IC chips has thermal modeling capabilities to check 'what-if' scenarios. Other EDA (Electronics Design and Automation and sometimes also used for Exploratory Data Analysis) tools are Allegro, Board Station, Expedition and CR5000.
• ECXML format for Thermal Simulations is equivalent to STEP format for CAD tools. The data from ICEPAK to FloTHERM can be transferred in ECXML format which is a vendor neutral format.
• DELPHI: Compact Thermal Model - the standard to create a thermal model for further use in thermal simulations

MOSFET

Reference: AN90003 - LFPAK MOSFET thermal design guide

• Part number BUK7M15-60E (LFPAK33, 15 mΩ, 60 V) the maximum thermal resistance junction to mounting base is 2.43 [K/W], the total thermal resistance, junction-to-ambient is 59.4 [K/W] when using 65.4 °C as (ambient) reference point.
• Part number BUK7S1R0-40H (LFPAK88, 1 mΩ, 40 V) the maximum thermal resistance junction to mounting base is 0.4 [K/W], the thermal resistance between mounting base and ambient is of much higher value (~ 30 K/W)

• Power Density, P_D: The power density of any device is the ratio of output power and the physical space it occupies. Thus, the unit of power density is [W/m³] or [W/cc].
• Efficiency, η: This is the ratio of output power and the input power. The loss of energy (or power) gets converted into heat. Hence, when power density is increased, the volume and surface area of MOSFET and any such device will decrease. To keep temperature rise of the system within permissible limit, the amount of heat dissipation has to be decreased which in turn require that the efficiency of the device must be increased.
• Heat dissipation: q = P_IN - P_OUT = h x A x [T_S - T_AMB] where h is the convective heat transfer coefficient of the surface exposed to cooling media, A is the skin (fluid-wetted) surface area, T_S is the surface temperature of the device casing and T_AMB is the bulk mean temperature of cooling media.
• Efficiency: η = P_OUT / P_IN = P_OUT / [P_OUT + q]
• η = 1 / [q/(V x P_D) + 1] where V = volume of the device
• η = 1 / [h x A x ΔT/(V x P_D) + 1] where ΔT = [T_S - T_AMB]
• 

The DSOP Advance package has a top source side cooling plate in addition to the bottom drain side plate as shown in Figure 2. These cooling plates contribute in reducing the thermal resistance (Rth).

At thermal equilibrium, the maximum power dissipation PD_MAX of a power MOSFET can be expressed in terms of the ambient temperature T_A, the maximum channel temperature T_CHMAX of the MOSFET and the channel-to-ambient thermal resistance R_THCH-A

• θ_i: Internal thermal resistance (channel-to-package)
• θ_b: External thermal resistance (package-to-ambient air), varies with the material and shape of the case and is significantly larger than θ_i, θ_c, θ_s and θ_f.
• θ_s: Thermal resistance of insulation shield
• θ_c: Contact thermal resistance (at the interface with a thermal fin)
• θ_f: Thermal resistance of the heat sink

A PCB trace is a thin line of conducting copper placed on a non-conductive base material usually called FR4 that carries the signal and power to the whole circuit. A copper trace has a specific width called trace width, and a particular thickness. The thickness of PCB is specified in ounce/ft² = 28.35 gm/ft² = 0.3052 [kg/m²] = 0.3042/8900 = 3.43 x 10^-5 [m] = 0.0343 [mm]. For typical PCBs, the most common copper thickness is specified as 35 [μm] which is equivalent to 1.0 [oz/ft²]. With electrical resistivity of 1.72 x 10^-8 [Ω.m] at 25 [°C] for copper, the electrical resistance per inch width per meter length of copper trace is 0.02 [Ω]. The electrical resistance per inch width per inch length of copper trace would be 0.50 [mΩ]. The resistance value shall increase in direct proportion of the length and inverse proportion of the width and/or thickness (mm or oz/ft²).

  For example, electrical resistance per inch width per inch length of copper trace having thickness of 2.0 [oz/ft²] would be 0.50 / 2 = 0.25 [mΩ]. Electrical resistance per 0.1 inch width per inch length of copper trace having thickness of 2.0 [oz/ft²] would be 0.50 / 2 / 0.1 = 2.5 [mΩ]. Electrical resistance per 0.1 inch width per meter length of copper trace having thickness of 1.0 [oz/ft²] would be 0.50 * 39.37 / 0.1 = 0.197 [Ω].

 With temperature coefficient of electrical resistance 0.0039 [1/K], electrical resistance per 0.1 inch width per meter length of copper trace having thickness of 1.0 [oz/ft²] at 100 [°C] would be 0.197 x [1 + 0.0039 x 75] = 0.255 [Ω]

Trace Heating: In the electrical wires the cooling rate initially increase with thickness of insulation, reaches a peak and then starts decreasing. Similarly, the temperature of traces are dependent on the board thickness, traces on top of a thin board get hotter than one on a thicker board. This is because a thicker board has higher cross-section for the heat to conduct through. Beyond a thickness of board, there is more material under the trace than the trace can efficiently utilize - the path to surface on which convection occurs gets longer - and hence there is no improvement in temperature or in fact the temperature of traces may increase further. PCB trace temperatures are very sensitive to thermal conductivity though the in-plane thermal conductivity has higher influence than through-plane value.

IDF and IDX: ECAD - EMN/EMP

1. EMN File Contains:
   • PCB Outline
   • Component Location
   • Component Orientation
   • Hole Information
   • Keep In and Keep Out Regions
2. EMP File Contains:
   • ECAD outlines for every component
   • ECAD component height information

There are many programs used to generate design of electronic items such as PCB and chips. Cadence, EasyEDA, Eagle, Altium Designer, Siemens Expedition Enterprise to name few. However, there is a need to have interface between ECAD and MCAD. This is accomplished by EMN and EMP files. The EMN file is related to the board and the EMP file is the library list of the components on the board. These files can generate a 3D view of the PCB Assembly. IDF files default to the following extensions: *.emn - neutral file of the board outline and component placement and *.emp - profile file that contains component outlines.. A sample EMN file commented with explanation of the information can be found here.

Reference: simplifiedsolutionsinc.com/images/Steps-to-create-3D-PCBs-in-ProE.pdf: In Pro/E (predecessor to Creo), there was an option to create an ecad_hint.map file which linked components in CAD Tool to 3D Pro/Engineer Model. When an IDF (emn) File is imported into Pro/Engineer, Pro/E cross-referenced the ecad_name and ecad_alt_name from the emn file against the ecad_hint.map. If a match was found, Pro/Engineer replaced "on the fly" geometry with a real 3D Pro/Engineer part or assembly. More information can be found at support.ptc.com/.../Map_File_Standard_Conventions.html

Sample ecad_hint.map file. Each section begins with the purpose, followed by '->'. Each section ends with 'end'. # is the comment character. Wildcard (*) is valid for 'all'. Object and value fields are separated by a space, spaces are permitted in value strings if the string is surrounded by quotation marks.

mcad_in_ignore ->
ecad_name "resistor"
ecad_alt_name "res_5"
ecad_type "part"
ref_des "*"
end

PWA = Printed Wiring Assemblies. Excerpts from "Intermediate Data Format Specification, Version 3.0": Structure of the Intermediate Data Format - The Intermediate Data Format consists of three files: the Board File, the Library File and the Panel File.

The Board File: It contains a description of a single PWA, including the board shape, layout restrictions and component placement.

The Library File: It contains descriptions of components used by one or more PWAs. *.emp is the extension of the library file.

The Panel File: It contains a description of a manufacturing panel including the panel shape, layout restrictions and the placement of boards and components on the panel.

The Panel File is an optional file, similar to the Board File, that contains the physical description of a manufacturing step-and-repeat panel and the locations of boards and components on that panel. The Panel File references one or more PWAs described in separate Board Files. Any component placed on the panel itself is referenced in a Library File.

The Gerber file

It is a connector and bridge between designers, engineers and PCB manufacturers. It needs to go through every manufacturing process and the factory can clearly define the customer's needs. According to UCAMCO (the company that currently owns the rights to Gerber File format): "Gerber file format" is a standard for PCB design data storage or transfer. Gerber file describes and communicates the constituents of a PCB image like the number of copper layers, solder masks and many others such attributes. Gerber files also act as input files to PCB printing devices like photo-plotters and Automated Optical Inspection (AOI) machines to print or compare circuit board images for different gadgets. Gerber files may also include metadata (data about other constituting data within a file) like solder mask, legend/silk and number of copper layers among other relevant printing information.

Following files comprise the full list of GERBER files which are usually zipped and shared to thermal simulation engineer or PCB Manufacturer.

"Electronic Schematics: Schematics communicate specific information about how electronics in a design should be connected to each other. Components are labeled with their electrical characteristics, such as capacitance or resistance, with the complete circuit being illustrated across the PCB. The schematic is an organized view of the electrical circuit and provides necessary information for manufacturing."

Typical *.emn File Entry

#------------------------------------------------------------------------------
#The comment character is the pound sign (#). A comment must be a separate line
#(record) and the comment character must be in column 1. Comments should be 
#located between, but not within sections of the IDF files.
#------------------------------------------------------------------------------
.HEADER
BOARD_FILE 3.0 "Sample File Generator" 2020/07/01.16:02:44 1
sample_board THOU
.END_HEADER
#Unit MM or THOU = milli-inch
#------------------------------------------------------------------------------
#Section keyord: .BOARD_OUTLINE or .PANEL_OUTLINE
#MCAD - Outline is owned by the Mechanical system and should not be modified in
#the Electrical system
#ECAD - Outline is owned by the Electrical system and should not be modified in 
#the Mechanical system
#UNOWNED - Outline can be modified in either system
#62.0 is thickness in milli-inch
#------------------------------------------------------------------------------
.BOARD_OUTLINE MCAD
62.0
0 5030.5 -120.0  0.0
0 5187.5 -120.0  0.0
0 5187.5  130.0  0.0
0 5155.0  130.0  0.0
0 5155.0  550.0 -180.0
...
.END_BOARD_OUTLINE
#------------------------------------------------------------------------------
.ELECTRICAL
EthnetBrd 135792468 THOU 59.0
0 -92.0  63.0 0
0 -92.0 -63.0 0
0  92.0 -63.0 0
0  92.0  63.0 0
0 -92.0  63.0 0
.END_ELECTRICAL
#------------------------------------------------------------------------------
EthnetBrd 135792468 E7
20.5 32.5 0.0 90.0 BOTTOM PLACED

• EthnetBrd is the ECAD name
• 135792468 is the ecad_alt_name (unique part number)
• E7 is the reference designator
• 20.5, 32.5 0.0 represent the location with respect to the origin of PCB (0,0) point X, Y, Z directions
• 90.0 represents the orientation of the component
• BOTTOM specifies the side of the PCB
• PLACED specifies component will be added to 3D PCB

These softwares are meant for electronics industry mainly and hence contains many built-in objects to expedite the simulation process. They can be summarized as follows:

• Primitive - Fundamental geometric entities in FloTHERM and ICEPAK: Cuboids, Prisms and Flow Resistances
• SmartPart - Object parametrically created out of Primitives: e.g. Enclosure, fan, PCB, cylinders, volume or surface heat source, heat sinks (described by base dimension, number of fins, fin width and fin height), perforated plate (fully designated by hole size and arrangement, pitch, free area ratio)
• Assembly - A group of Primitives, SmartParts and Sub-Assemblies
• Attribute - A property that can be attached to Primitives and SmartParts (e.g. material properties)

Reading Mechanical CAD (MCAD) data

• The MCAD data can be read either in their native format such as ProE, Solidworks or CATIA files (parts and assemblies) or neutral formats such as IGES, STEP or PARASOLID.
• After initial defeaturing (removal of chamfers and fillets) and simplifications (removal of small holes, branding logos, part identifiers), the MCAD geometry needs to be converted into ICEPAK / FloTHERM entities.
• Simplification is permissible to the to the extent where the geometry could be created manually using primitives and smart-parts in ICEPAK / FloTHERM!
• The conversion into ICEPAK / FloTHERM entities is a process of replacing a detailed geometry say perforated plate with a plate of same size without perforation and specifying the perforation details as attributes to the ICEPAK / FloTHERM entities.

Mesh generation process and recommendations

• For naturally convected cases, the computational domain needs to be made bigger than the chassis or the board.
• For the space above the chassis extend the domain 2~3 × height of chassis. Note that the buoyancy may not be strong enough to establish a flow from lower face to upper face and reverse flow can be observed on both of these faces. In order to reduce the reverse flows, the domain boundaries may need to be kept closer to the heat source.
• For space below chassis extend the domain equal to the height of chassis.
• For the remaining sides (front, rear, left and right) of the chassis, extend the domain 0.5 ~ 1.0 × depth and width of the chassis.
• In case on natural convection, the heat transfer through convection is low and hence radiation also contributed significantly. Up to 50% of heat transfer is by radiation and remaining 50% by natural convection.This can be justified by the fact that the HTC value for natural convection in air varies between 5~10 [W/m².K] whereas equivalent HTC for radiative heat transfer = ε × σ × (T_WALL⁴ - T_AMB⁴) / (T_WALL - T_AMB) = 4.9 [W/m².K] for ε = 0.5, T_WALL = 100 [°C] and T_AMB = 50 [°C].
• The components are mostly represented as volume with sharp corners such as cuboid and rectangles. A cut-cell method also known as trimmer mesh or Cartesian mesh or snappyHexMesh (in OpenFOAM) is used in ICEPAK and FloTHERM.
• For printed circuit boards as in any surface with a significant amount of heat flux, 3 cells in the first millimeter above the board (air volume) and 3 cells in the first millimeter below the board (solid volume) is recommended.
• Maintain aspect ratio of cells < 100.
• For fins, maintain > 5 cells cross a channel for better heat transfer and pressure drop prediction, use two or more cells across the thickness in the solid.

Special applications in Electronic Cooling

• Thermo-Electric Cooling (TEC): This device is based on Peltier effect where thermal energy is absorbed at one dissimilar metal junction and discharged at the other junction when electric current flows within a closed circuit. It comprises of p-type and n-type semiconductors sandwiched between ceramic electrical insulators. TEC are solid state heat pumps for applications where cooling below ambient are required. The cold junction acts as 'evaporator' and hot junction as 'condenser' of a refrigeration cycle.

  

  • Seebeck Effect: ΔV = α × (T_H - T_C) where α [V/K] = differential Seebeck coefficient or (thermo electric power coefficient) between the two materials, positive when the direction of electric current is same as the direction of heat flow.
  • Q_H [W] = β [V] × I [A] where β is differential Peltier coefficient between given two materials
  • β < 0: Electric current and heat flow in opposite directions
  • β > 0: Electric current and heat flow in same directions
  • COP = coefficient of performance of the thermoelectric device = Q_C / J, which typically is between 0.4 and 0.7 for single stage applications.
• Heat Pipe: Capillary effect and phase change (evaporation and condensation) are the phenomena which define operation of heat pipes. Due to phase change from liquid to vapour, the heat transfer coefficient for heat pipes is extremely high - of the order of 40,000 [W/m².K]. Originally invented by NASA for space application, it has gained widespread application in electronics industry.

  

  

• Heat Spreader: This is an application similar to heat sink. The purpose of a heat spreader is to use material with a very high thermal conductivity such as graphite with k = 1400 [W/m-K] to make the heat flow in-plane over a larger area so that it can be further dissipated into ambient using heat sinks.
• PCM - Phase Change Material: These are energy storage and release mechanism based on change of phase (typically solidification and melting). The material can be used to keep temperature fluctuations low in case of heating and cooling cycles. Sometimes, the PCM can also act as an insulator to heat dissipation based on thermal conductivity. Some key characteristics required for a energy storage and release type PCM are tabulated below.

  Characterisitcs	Desired value	Remark
  Melting point, TMP	As per temperature control	Selection of material will depend on temperature to be maintained
  Specific heat capacity, Cp	High	Energy storage capacity ∝ Cp. Higher the Cp, lesser the mass required to store a given amount of energy.
  Density, ρ	High	Energy storage capacity ∝ ρ and the volume required is also less as m = ρ * V
  Thermal Conductivity, k	High for energy storage purpose	Low value is required for insulation where heat is to be maintained near the source itself
  Coefficient of volume expansion, γ	Low	This governs flexibility or void space required in the storage container
  Chemical compatibility	Non-corrosive	Should not react with the container and other materials in case of leaks
  Thermal cycling (heating-cooling) stability	No degradation	The micro-structure and material properties should not degrade with heating-cooling cycles

TEC Performance Calculation

Field Variables

1. i = Current [A]
2. k = Thermal conductivity of TEC block [W/m-K]
3. Q_H = heat rejection from hot surface (the 'condenser') [W]
4. Q_C = heat absorption by cold surface (the 'evaporator') [W]
5. R = Electric Resistance of TEC assembly [Ω]
6. T_C = cold side temperature (the 'evaporator') [K]
7. T_H = hot side temperature (the 'condenser') [K]
8. P = power consumption by TEC device = (Q_H - Q_L) [W]
9. S = seebeck co-efficient [V/K]
10. ΔT = temperature difference between hot and cold junction [K]
11. G = Ratio of cross-section area to the length (thickness) of the device [m]
12. ρ = resistivity of TEC device [Ω-m]
13. COP = Coefficient of Performance = Q_C / P

Or

Q_C = -[S.i.T_C - 0.5 × i²ρ/G − k×G×(T_H − T_C)]

Similarly:

Or

Q_C = [S.i.T_H + 0.5 × i²ρ/G − k×G×(T_H − T_C)]

Orthotropic conductivity based on lumped block assumptions. 10% Copper is a reasonable guess. In case one needs to use "Locally Varying Orthotropic" thermal conductivity, the detail layout of traces and FR4 layers need to be modelled.

• k_{IN_PLANE} = VF_Cu × k_Cu + (1-VF_Cu) × k_Die
• 1/k_{X_PLANE} = VF_Cu / k_Cu + (1-VF_Cu) / k_Die
• Here, VF = Volume Fraction of copper in fractions (that is the value lies between 0 and 1).

k_{LAYER_i} = k_Cu × A_Cu / A_PCB + k_FRP × A_FRP / A_PCB

ICEPAK is a GUI for pre- and post-processing. It uses FLUENT as solver and in this process many files get created. Following is a list of files and its owner (ICEPAK or FLUENT?).

Few keyboard short-cuts and special topics in ICEPAK

• Move legend with Ctrl and the middle mouse button
• Edit levels and set orientation with shift right-click on legend
• Move the cut-plane in the domain with shift and the middle mouse button
• Shift middle-click on CAD objects to graphically move the CAD geometry
• Thermal Chokepoint: the dot product of heat flux and temperature gradient - it shows regions of high heat flux experiencing large thermal resistances
• Thermal Cross: the cross product of heat flux and temperature gradient - it shows regions where large heat flux vectors not aligned with high thermal gradients

Basic Solver Setting

Mesh Generation

Fan, Fins and Grilles

Boundary Conditions

Monitors and Runs Settings

Micro-Channels

Heat Transfers from Extended Surfaces (Fins)

Such fins are extruded or machined and needs to be fixed on the heat generating component using adhesive or screws. This creates a thermal contact resistance and needs to be accounted for temperature calculation of the mating surfaces. The parameter ΔT/[Q.A] can be used in fin selection for given heat dissipation and surface area (available space). Lower the number, better the heat sink design.

The heat transfer rate of pin-type fin for natural convection in air is tabulated below. Note the impact of L/D ratio on heat transfer rate.

The values for forced convection in air is tabulated below. 'A' is the heat transfer area of the fin and not the cross-section area. The parameter ΔT/[Q.A] can be used in fin selection for given heat dissipation and surface area (available space). For example, for a heat dissipation of 10 [W] using a fin of diameter 20 [mm] and height 100 [mm], the expected increase in temperature of the base of fin is 10 [W] x 62.8 [cm²] x 0.1431 = 89.9 [K].

More on LED

Thermal Simulations in Data Centres